2013 IEEE VLSI PROJECTS

                                        IEEE 2013 VLSI PROJECTS

1. A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits.

2. VLSI Architecture of Arithmetic Coder Used in SPIHT.

3. Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes.

4. Area-Delay Efficient Binary Adders in QCA.

5. Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip.

6. Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure.

7. VLSI Implementation of a Low-Cost High-Quality Image Scaling Processor.

8. A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing.

9. Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops.

10. FPGA Implementation of FFT Algorithm for IEEE 802.16e (Mobile WiMAX).

11. Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based Residue Number System.

12. Design of Testable Reversible Sequential Circuits.

13. Glitch-Free NAND-Based Digitally Controlled Delay-Lines.

14. The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures.

15. Time-Based All-Digital Technique for Analog Built-in Self-Test.

16. Broadside and Skewed-Load Tests Under Primary Input Constraints.

17. Active Filter-Based Hybrid On-Chip DC–DC Converter for Point-of-Load Voltage Regulation.

18.A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks.

19. An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform.

20. Pipelined Parallel FFT Architectures via Folding Transformation.